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- #ifndef __VO2_H__
- #define __VO2_H__
-
- /*
- * vo2.h
- *
- * headers/defines (internal, not shipped) for Sirius video board
- *
- * Copyright 1993, Silicon Graphics, Inc.
- * All Rights Reserved.
- *
- * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics, Inc.;
- * the contents of this file may not be disclosed to third parties, copied or
- * duplicated in any form, in whole or in part, without the prior written
- * permission of Silicon Graphics, Inc.
- *
- * RESTRICTED RIGHTS LEGEND:
- * Use, duplication or disclosure by the Government is subject to restrictions
- * as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
- * and Computer Software clause at DFARS 252.227-7013, and/or in similar or
- * successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
- * rights reserved under the Copyright Laws of the United States.
- */
- #include <sys/time.h>
- #define VO2_BOARDNAME "Sirius"
- #define VO2_VERSION_NUMBER 111
-
- #define VO2_BDREV_MINIMUM 3
- #define VO2_BDREV_ADDED_XTALS 4
-
- #define VO2_SPL spl5
-
- /*
- * Machine type
- */
- #ifdef IP5
- #define MPBUS
- #endif
- #ifdef IP17
- #define MPBUS
- #endif
- #ifdef IP19
- #define ONYX
- #endif
- #ifdef IP21
- #define ONYX
- #endif
-
- /*
- * Directly accessible registers (on the VME bus)
- */
-
- #define _VO2_BASE 0x0
-
- #define _VO2_ID_REG (_VO2_BASE+0x00)
- #define _VO2_VME_CMD (_VO2_BASE+0x04)
- #define _VO2_CNTRL (_VO2_BASE+0x08)
- #define _VO2_DMA_BLKSIZ (_VO2_BASE+0x0C)
- #define _VO2_INT_STAT (_VO2_BASE+0x10)
- #define _VO2_INT_MASK (_VO2_BASE+0x14)
- #define _VO2_INT_MODE (_VO2_BASE+0x18)
- #define _VO2_LOC_ADDR (_VO2_BASE+0x1C)
- #define _VO2_LOC_DATA (_VO2_BASE+0x20)
- #define _VO2_XILINX_CNTRL (_VO2_BASE+0x24)
- #define _VO2_XILINX_DATA (_VO2_BASE+0x28)
- #define _VO2_JTAG_MAIN (_VO2_BASE+0x2C)
- /*
- * _VO2_JTAG_PAB occupies bits [1..0] of _VO2_BASE+0x30;
- * _VO2_VLAN_ADDR occupies bits [3..2] of _VO2_BASE+0x30.
- */
- #define _VO2_JTAG_PAB (_VO2_BASE+0x30)
- #define _VO2_VLAN_ADDR (_VO2_BASE+0x30)
- #define _VO2_VLAN_DATA (_VO2_BASE+0x34)
-
- /*
- * The VLAN controller is accessed by reading and writing the
- * _VO2_VLAN_DATA register. The data read from that location is
- * one of the three possible _VO2_VLAN_ADDR locations:
- *
- * (a) _VO2_VLAN_DATA_TX_RX (the data transceiver, read/write 8 bits)
- * (b) _VO2_HOST_TO_VLAN_FLAG (vlan busy flag; cleared when vlan reads byte)
- * (c) _VO2_VLAN_TO_HOST_FLAG (host busy flag; cleared when host reads byte)
- */
-
- #define _VO2_LAST_REG _VO2_VLAN_DATA
-
- #define _VO2_VLAN_DATA_TX_RX (0x0 << 2)
- #define _VO2_HOST_TO_VLAN_FLAG (0x2 << 2)
- #define _VO2_VLAN_TO_HOST_FLAG (0x3 << 2)
-
- #define _VO2_VLAN_BUSY 0x1
- #define _VO2_HOST_BUSY 0x1
-
- #if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
-
- struct vo2_board {
- volatile unsigned int id_reg;
- volatile unsigned int vme_cmd;
- volatile unsigned int cntrl;
- volatile unsigned int dma_blksiz;
- volatile unsigned int int_stat;
- volatile unsigned int int_mask;
- volatile unsigned int int_mode;
- volatile unsigned int loc_addr;
- volatile unsigned int loc_data;
- volatile unsigned int xilinx_cntrl;
- volatile unsigned int xilinx_data;
- volatile unsigned int jtag_main;
- volatile unsigned int jtag_pab;
- };
-
- typedef struct vo2_board *vo2_board_t;
-
- #endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
-
- /*
- * What's in those registers
- */
-
- /* _VO2_ID_REG - ID register */
- #define _VO2_ID_MASK 0x00ffffff
- #define _VO2_ID_VALUE 0x00bcdef0
- #define _VO2_HWREV_SHIFT 24
- #define _VO2_HWREV_MASK 0x0f000000
-
- /* _VO2_VME_CMD - VME command register (write only)
- * fifo of up to _VO2_VME_STK_SIZE words
- * first word: made from _VO2_VME_CMD0 parts
- * second word: host memory address (for all except _VO2_VME_CMD0_INT)
- * third word: see _VO2_LADDR_* below (all dma except _VO2_VME_CMD0_VID)
- */
- #define _VO2_VME_STK_SIZE 16
-
- #define _VO2_VME_CMD0_N_SHIFT 0
- #define _VO2_VME_CMD0_N_MASK 0x00007fff
-
- #define _VO2_VME_CMD0_SHIFT 15
- #define _VO2_VME_CMD0_MASK 0x00078000
-
- #define _VO2_VME_CMD0_NOP 0x00000000
- #define _VO2_VME_CMD0_VID 0x00008000
- #define _VO2_VME_CMD0_VLIST0 0x00010000
- #define _VO2_VME_CMD0_VLIST1 0x00018000
- #define _VO2_VME_CMD0_VLIST2 0x00020000
- #define _VO2_VME_CMD0_VLIST3 0x00028000
- #define _VO2_VME_CMD0_INT 0x00030000
- #define _VO2_VME_CMD0_DMA 0x00038000
-
- #define _VO2_VME_CMD0_D32 0x00000000
- #define _VO2_VME_CMD0_D64 0x00080000
- #define _VO2_VME_CMD0_RD 0x00000000
- #define _VO2_VME_CMD0_WR 0x00100000
-
- #define _VO2_VME_CMD0_BLK_SHIFT 21
- #define _VO2_VME_CMD0_BLK_MASK 0xffe00000
-
- /* _VO2_CNTRL - control (and status) register */
- #define _VO2_RESET 0x00000001
- #define _VO2_RESET_VLIST 0x00000002
- #define _VO2_RESET_DMA 0x00000004
- #define _VO2_DMA_ROR 0x00000000
- #define _VO2_DMA_RWD 0x00000008
- #define _VO2_JTAG_ENABLE 0x00000010
- #define _VO2_VLIST_BUSY 0x00000020
- #define _VO2_SD1_INSTALLED_L 0x00000040
- #define _VO2_PAB_CTRL_L 0x00000080
- #define _VO2_PAB_DATA_L 0x00000100
- #define _VO2_CNTRL_UNUSED_9 0x00000200
- #define _VO2_BOB_POWER_L 0x00000400
- #define _VO2_BOB_CABLE_L 0x00000800
-
- /* _VO2_DMA_BLKSIZ - mode register */
-
- /* _VO2_INT_STAT - interrupt status register (read only) */
- /* _VO2_INT_MASK - interrupt mask register */
- #define _VO2_INT_ANY 0xffffff80
- #define _VO2_INT_FRMDRP_CP 0x00000080
- #define _VO2_INT_FRMDRP_ALPHA 0x00000100
- #define _VO2_INT_FRMREP_ALPHA 0x00000200
- #define _VO2_INT_INT0 0x00000400
- #define _VO2_INT_INT1 0x00000800
- #define _VO2_INT_INT2 0x00001000
- #define _VO2_INT_INT3 0x00002000
- #define _VO2_INT_VLIST0 0x00004000
- #define _VO2_INT_VLIST1 0x00008000
- #define _VO2_INT_VLIST2 0x00010000
- #define _VO2_INT_VLIST3 0x00020000
- #define _VO2_INT_FRMDRP_A 0x00040000
- #define _VO2_INT_FRMDRP_B 0x00080000
- #define _VO2_INT_FRMREP_A 0x00100000
- #define _VO2_INT_FRMREP_B 0x00200000
- #define _VO2_INT_NOSYNC_D1_1 0x00400000
- #define _VO2_INT_NOSYNC_D1_2 0x00800000
- #define _VO2_INT_NOSYNC_VI 0x01000000
- #define _VO2_INT_NOSYNC_VO 0x02000000
- #define _VO2_INT_NOGEN_VI 0x04000000
- #define _VO2_INT_NOGEN_VO 0x08000000
- #define _VO2_INT_VLAN 0x10000000
- #define _VO2_INT_GPI_2 0x20000000
- #define _VO2_INT_GPI_1 0x40000000
- #define _VO2_INT_VME_CNTRL 0x80000000
-
- /* _VO2_INT_MODE - interrupt mode register */
- #define _VO2_IACK_MASK 0x000000ff
- #define _VO2_ILEV_MASK 0x00000300
- #define _VO2_ILEV_SHIFT 8
- #define _VO2_ILEV_MIN 4
- #define _VO2_ILEV_MAX 7
-
- /* _VO2_LOC_ADDR - local address register (vlist must be idle) */
- #define _VO2_LADDR_MASK 0x0003ffff
- #define _VO2_LADDR_SHIFT 0
- #define _VO2_LADDR_SPEED_FAST 0x00000000
- #define _VO2_LADDR_SPEED_MEDF 0x00040000
- #define _VO2_LADDR_SPEED_MEDS 0x00080000
- #define _VO2_LADDR_SPEED_SLOW 0x000c0000
- #define _VO2_LADDR_SPEED_MASK 0x000c0000
- #define _VO2_LADDR_SPEED_SHIFT 18
- #define _VO2_LADDR_INCR 0x00100000
-
- /* _VO2_LOC_DATA - local data register (vlist must be idle) */
-
- /* _VO2_XILINX_CNTRL - xilinx control register */
- #define _VO2_XILINX_PGM 0x00000001
- #define _VO2_XILINX_RD 0x00000002
- #define _VO2_XILINX_DONE 0x00000004
-
- /* _VO2_XILINX_DATA - xilinx data register */
- #define _VO2_XILINX_DATA_MASK 0x00000001
-
- /* _VO2_JTAG_MAIN - jtag control register for the VO2 scan chain*/
- /* _VO2_JTAG_PAB - jtag control register for the paddleboard scan chain*/
- #define _VO2_JTAG_TDIO 0x00000001
- #define _VO2_JTAG_TMS 0x00000002
-
- /*
- * end of directly accessible registers
- */
-
- /*
- * vlist definitions
- */
- #define _VO2_VLIST_DATA_MASK 0x3fffffff
- #define _VO2_VLIST_CMD_MASK 0xc0000000
- #define _VO2_VLIST_WRDATA 0x00000000
- #define _VO2_VLIST_WRADDR 0x40000000
- #define _VO2_VLIST_WAIT_UNCOND 0x80000000
- #define _VO2_VLIST_WAIT_COND 0x80100000
- #define _VO2_VLIST_DONE 0xc0000000
-
- #define _VO2_VLIST_DEFAULT 0
-
- #define _VO2L_VLIST_0_SIZE 0x2400
- #define _VO2L_VLIST_1_SIZE 0x2400
- #define _VO2L_VLIST_2_SIZE 0x2400
- #define _VO2L_VLIST_3_SIZE 0x1400
-
- /*
- * Local bus address definitions
- */
- #define _VO2L_VLIST_0_RAM (0x00000 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_VLIST_1_RAM (0x02400 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_VLIST_2_RAM (0x04800 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_VLIST_3_RAM (0x06c00 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_D1_OUT_LUT_YUV (0x08000 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_D1_OUT_LUT_ALPHA (0x0a000 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_CKG_LUT (0x0c000 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_AOUT_LUT_YUV (0x0e000 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_AOUT_LUT_ALPHA (0x10000 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_VLIST_DUR0 (0x13400 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_VLIST_DUR1 (0x13401 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_VLIST_DUR2 (0x13402 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_VLIST_VL0SEL (0x13404 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_VLIST_VL1SEL (0x13405 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_VLIST_VL2SEL (0x13406 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_VLIST_EN (0x13407 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBA_SRC_DST_SEL (0x13800 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBA_STATUS (0x13801 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBA_COMMAND (0x13801 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBA_UPPER_LEFT_VID_X (0x13802 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBA_UPPER_LEFT_Y (0x13803 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBA_PIX_PER_LIN (0x13804 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBA_LIN_PER_FLD (0x13805 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBA_UPPER_LEFT_ALP_X (0x13806 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBA_EAV_DELAY (0x13807 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBA_OVER_READ (0x13808 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBA_CLK_PLL_CTL_REG3 (0x13809 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBA_OUT_PIPE_DLY (0x1380a |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBA_FIELD_DOMINANCE (0x1380b |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBA_CLK_PLL_CTL_REG1 (0x1380c |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBA_CLK_PLL_CTL_REG2 (0x1380d |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBB_SRC_DST_SEL (0x13c00 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBB_STATUS (0x13c01 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBB_COMMAND (0x13c01 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBB_UPPER_LEFT_VID_X (0x13c02 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBB_UPPER_LEFT_Y (0x13c03 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBB_PIX_PER_LIN (0x13c04 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBB_LIN_PER_FLD (0x13c05 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBB_UPPER_LEFT_ALP_X (0x13c06 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBB_EAV_DELAY (0x13c07 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBB_OVER_READ (0x13c08 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBB_CLK_PLL_CTL_REG3 (0x13c09 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBB_OUT_PIPE_DLY (0x13c0a |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBB_FIELD_DOMINANCE (0x13c0b |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBB_CLK_PLL_CTL_REG1 (0x13c0c |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBB_CLK_PLL_CTL_REG2 (0x13c0d |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBA_ALPHA_SRC_DST_SEL (0x14000 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBA_ALPHA_STATUS (0x14001 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBA_ALPHA_COMMAND (0x14001 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBA_ALPHA_UPPER_LEFT_VID_X (0x14002 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBA_ALPHA_UPPER_LEFT_Y (0x14003 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBA_ALPHA_PIX_PER_LIN (0x14004 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBA_ALPHA_LIN_PER_FLD (0x14005 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBA_ALPHA_UPPER_LEFT_ALP_X (0x14006 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBA_ALPHA_EAV_DELAY (0x14007 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBA_ALPHA_OVER_READ (0x14008 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBA_ALPHA_CLK_PLL_CTL_REG3 (0x14009 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBA_ALPHA_OUT_PIPE_DLY (0x1400a |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBA_ALPHA_FIELD_DOMINANCE (0x1400b |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBA_ALPHA_CLK_PLL_CTL_REG1 (0x1400c |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBA_ALPHA_CLK_PLL_CTL_REG2 (0x1400d |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBA_MATRIX_COEF (0x14400 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_FBB_MATRIX_COEF (0x14800 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_CKG_MATRIX_COEF (0x14c00 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_CP_MATRIX_COEF (0x15000 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_VIDOUT_MATRIX_COEF (0x15400 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_PACTL (0x15800 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_PACTL_MODE (0x15800 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_PACTL_HI_XSTART (0x15801 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_PACTL_HI_XPIXEL_LINE (0x15802 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_PACTL_HI_YSTART (0x15803 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_PACTL_HI_YLINES_FRAME (0x15804 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_PACTL_LO_XPIXEL_LINE (0x15805 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_PACTL_LO_YLINES_FIELD (0x15806 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_PACTL_CLOCK_CTL1 (0x15807 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_PACTL_CLOCK_CTL2 (0x15808 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_PACTL_HI_XYCLEAR (0x15809 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_PA_RGBA_DATA (0x15c00 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_PA_RGBA_ADDR (0x15c01 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_PA_RED_DATA (0x16000 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_PA_RED_ADDR (0x16001 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_PA_GREEN_DATA (0x16400 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_PA_GREEN_ADDR (0x16401 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_PA_BLUE_DATA (0x16800 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_PA_BLUE_ADDR (0x16801 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_PA_ALP_DATA (0x16c00 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_PA_ALP_ADDR (0x16c01 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_AP_RGBA_DATA (0x17000 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_AP_RGBA_ADDR (0x17001 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_AP_RG_DATA (0x17400 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_AP_RG_ADDR (0x17401 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_AP_BA_DATA (0x17800 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_AP_BA_ADDR (0x17801 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_AP_RED_DATA (0x17c00 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_AP_RED_ADDR (0x17c01 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_AP_GREEN_DATA (0x18000 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_AP_GREEN_ADDR (0x18001 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_AP_BLUE_DATA (0x18400 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_AP_BLUE_ADDR (0x18401 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_AP_ALP_DATA (0x18800 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_AP_ALP_ADDR (0x18801 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_DR_RGBA_DATA (0x18c00 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_DR_RGBA_ADDR (0x18c01 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_DR_RG_DATA (0x19000 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_DR_RG_ADDR (0x19001 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_DR_BA_DATA (0x19400 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_DR_BA_ADDR (0x19401 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_DR_RED_DATA (0x19800 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_DR_RED_ADDR (0x19801 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_DR_GREEN_DATA (0x19c00 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_DR_GREEN_ADDR (0x19c01 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_DR_BLUE_DATA (0x1a000 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_DR_BLUE_ADDR (0x1a001 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_DR_ALP_DATA (0x1a400 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_DR_ALP_ADDR (0x1a401 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_CP_CONTROLLER (0x1a800 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_CTL_REG1 (0x1ac00 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_CTL_REG2 (0x1b000 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_EEPROM_DEFUNCT (0x1b400 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_D1_1_CS (0x1b400 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_ENC_CTL_ADDR (0x1b800 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_ENC_LUT_ADDR (0x1b801 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_ENC_CTL_DATA (0x1b802 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_ENC_LUT_DATA (0x1b803 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_VLAN (0x1bc00 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_PAB_RD (0x1c000 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_ANLG_CTL_REG (0x1c400 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_CALDAC_A_LD (0x1c800 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_CALDAC_B_LD (0x1cc00 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_CALDAC (0x1d000 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_DEC_ADDR (0x1d400 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_DEC_DATA (0x1d402 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_GENIN_R0 (0x1d800 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_GENIN_R1 (0x1d801 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_GENIN_R2 (0x1d802 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_GENIN_R3 (0x1d803 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_GENIN_R4 (0x1d804 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_GENOUT_R0 (0x1dc00 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_GENOUT_R1 (0x1dc01 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_GENOUT_R2 (0x1dc02 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_GENOUT_R3 (0x1dc03 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_GENOUT_R4 (0x1dc04 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_GEN_ENC (0x1e000 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_GEN_ENC_LOAD (0x1e001 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_STATUS (0x1e400 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_D1_2_CS (0x1e800 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_VOF (0x1ec00 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_VL0INT (0x1f000 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_VL1INT (0x1f400 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_VL2INT (0x1f800 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_VL3INT (0x1fc00 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_XILINX_CCK (0x20000 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_CTL_REG3 (0x20400 |_VO2_LADDR_SPEED_SLOW)
- #define _VO2L_EEPROM (0x20800 |_VO2_LADDR_SPEED_SLOW)
-
- /*
- * Control register bit definitions on the local bus
- */
-
- /*
- * _VO2L_CTL_REG1
- */
- #define _VO2L_CTL_REG1_UNUSED_0 0x00000001
- #define _VO2L_CTL_IN_CH2_PARALLEL 0x00000002
- #define _VO2L_CTL_EN_BURST_LOCK_OUTCLK 0x00000004
- #define _VO2L_CTL_IN_CH1_PARALLEL 0x00000008
- #define _VO2L_CTL_4444_SEL_CS 0x00000010
- #define _VO2L_CTL_REG1_UNUSED_5 0x00000020
- #define _VO2L_CTL_SEL_FBA_VID_CLK0 0x00000040
- #define _VO2L_CTL_SEL_FBA_VID_CLK1 0x00000080
- #define _VO2L_CTL_SEL_FBA_VID_CLK2 0x00000100
- #define _VO2L_CTL_SEL_FBA_ALP_CLK0 0x00000200
- #define _VO2L_CTL_SEL_FBA_ALP_CLK1 0x00000400
- #define _VO2L_CTL_SEL_FBA_ALP_CLK2 0x00000800
- #define _VO2L_CTL_VDR_DELAY 0x00001000
- #define _VO2L_CTL_SEL_FBB_CLK0 0x00002000
- #define _VO2L_CTL_SEL_FBB_CLK1 0x00004000
- #define _VO2L_CTL_SEL_FBB_CLK2 0x00008000
- #define _VO2L_CTL_VIDOUT_MTX_BYP_DIG 0x00010000
- #define _VO2L_CTL_VIDOUT_MTX_BYP_ANLG 0x00020000
- #define _VO2L_CTL_VIDOUT_LUT_BANK1 0x00040000
- #define _VO2L_CTL_VLAN_RESET_L 0x00080000
- #define _VO2L_CTL_SEL_CKG_ALP_FBA 0x00100000
- #define _VO2L_CTL_SEL_CKG_ALP_FBB 0x00200000
- #define _VO2L_CTL_CKG_LUT_BANK1 0x00400000
- #define _VO2L_CTL_VME_10BITS 0x00800000
- #define _VO2L_CTL_VME_2PIXFER 0x01000000
- #define _VO2L_CTL_VDR_OFFSET_SELECT 0x02000000
- #define _VO2L_CTL_FBA_VID_CLK_TEST 0x04000000
- #define _VO2L_CTL_FBA_ALP_CLK_TEST 0x08000000
- #define _VO2L_CTL_FBB_CLK_TEST 0x10000000
- #define _VO2L_CTL_OUT_CLK_TEST 0x20000000
-
- /*
- * _VO2L_CTL_REG1 mask defines. This defines the FBA/FBB/FBA_ALPHA
- * clock bit masks.
- */
- #define _VO2L_CTL_SEL_FBA_VID_CLK 0x000001c0
- #define _VO2L_CTL_SEL_FBA_ALP_CLK 0x00000e00
- #define _VO2L_CTL_SEL_FBB_VID_CLK 0x0000e000
-
- /*
- * _VO2L_CTL_REG shift defines for input clock select
- */
- #define _VO2L_CTL_SHIFT_4444_SEL 0x4
- #define _VO2L_CTL_SHIFT_FBA_VID_CLK 0x6
- #define _VO2L_CTL_SHIFT_FBA_ALP_CLK 0x9
- #define _VO2L_CTL_SHIFT_FBB_VID_CLK 0xd
-
- /*
- * _VO2L_CTL_REG1 Value defines.
- */
- #define _VO2L_CTL_BURST_ON 0x04
- #define _VO2L_CTL_BURST_OFF 0x00
-
- /*
- * _VO2L_CTL_REG2
- */
- #define _VO2L_CTL_VIDOUT_FILT_BYP 0x00000001
- #define _VO2L_CTL_VIDOUT_FILT_TCO 0x00000002
- #define _VO2L_CTL_VIDOUT_FILT_RND0 0x00000004
- #define _VO2L_CTL_VIDOUT_FILT_RND1 0x00000008
- #define _VO2L_CTL_VIDOUT_FILT_RND2 0x00000010
- #define _VO2L_CTL_FBA_VID_BC_PROG_L 0x00000020
- #define _VO2L_CTL_FBA_ALP_PROG_L 0x00000040
- #define _VO2L_CTL_FBB_BC_PROG_L 0x00000080
- #define _VO2L_CTL_CF_PROG_L 0x00000100
- #define _VO2L_CTL_CKG_PROG_L 0x00000200
- #define _VO2L_CTL_FBA_CRX_PROG_L 0x00000400
- #define _VO2L_CTL_FBB_CRX_PROG_L 0x00000800
- #define _VO2L_CTL_D1_CH1_PROG_L 0x00001000
- #define _VO2L_CTL_D1_CH2_PROG_L 0x00002000
- #define _VO2L_CTL_D1_OUT_PROG_L 0x00004000
- #define _VO2L_CTL_GENIN_PROG_L 0x00008000
- #define _VO2L_CTL_GENOUT_PROG_L 0x00010000
- #define _VO2L_CTL_PACTL_PROG_L 0x00020000
- #define _VO2L_CTL_VDR_PROG_L 0x00040000
- #define _VO2L_CTL_VOF_PROG_L 0x00080000
- #define _VO2L_CTL_FBA_FILT_BYP 0x00100000
- #define _VO2L_CTL_FBA_FILT_TCO 0x00200000
- #define _VO2L_CTL_FBA_FILT_RND0 0x00400000
- #define _VO2L_CTL_FBA_FILT_RND1 0x00800000
- #define _VO2L_CTL_FBA_FILT_RND2 0x01000000
- #define _VO2L_CTL_FBB_FILT_BYP 0x02000000
- #define _VO2L_CTL_FBB_FILT_TCO 0x04000000
- #define _VO2L_CTL_FBB_FILT_RND0 0x08000000
- #define _VO2L_CTL_FBB_FILT_RND1 0x10000000
- #define _VO2L_CTL_FBB_FILT_RND2 0x20000000
-
- /*
- * CTL_REG2 shift values
- */
- #define _VO2L_CTL_SHIFT_VIDOUT_FILT 0
- #define _VO2L_CTL_SHIFT_FBA_FILT 20
- #define _VO2L_CTL_SHIFT_FBB_FILT 25
-
- /*
- * _VO2L_CTL_REG3.
- */
- #define _VO2L_CTL_REG3_UNUSED_0 0x00000001
- #define _VO2L_CTL_FBA_CRX_SCK 0x00000002
- #define _VO2L_CTL_FBB_CRX_SCK 0x00000004
- /*
- * <CTL1> <CTL0> MODE
- * 0 0 RGBA12
- * 0 1 RGB5 Tex
- * 1 0 RGBA4 Tex
- * 1 1 RGBA8 Tex
- */
- #define _VO2L_CTL_CP_CTL0 0x00000008
- #define _VO2L_CTL_CP_CTL1 0x00000010
- #define _VO2L_CTL_CP_CTL_F1_DOM 0x00000020
- #define _VO2L_CTL_CP_CTL_OFFSET 0x00000040
- #define _VO2L_CTL_CP_FIELDS 0x00000080
- #define _VO2L_CTL_CP_BRD_ID0 0x00000100
- #define _VO2L_CTL_CP_BRD_ID1 0x00000200
- #define _VO2L_CTL_GPI_CNTL_CH1_0 0x00000400
- #define _VO2L_CTL_GPI_CNTL_CH1_1 0x00000800
- #define _VO2L_CTL_GPI_CNTL_CH2_0 0x00001000
- #define _VO2L_CTL_GPI_CNTL_CH2_1 0x00002000
- #define _VO2L_CTL_ALPOUT_L0 0x00004000
- #define _VO2L_CTL_ALPOUT_L1 0x00008000
- #define _VO2L_CTL_ALPOUT_L2 0x00010000
- #define _VO2L_CTL_ALPOUT_L3 0x00020000
-
- /*
- * _VO2L_CTL_REG3 mask defines.
- */
- #define _VO2L_CTL_CP_CTL 0x00000018
- #define _VO2L_CTL_CP_BRD_ID 0x00000300
- #define _VO2L_CTL_GPI_CNTL_CH1 0x00000c00
- #define _VO2L_CTL_GPI_CNTL_CH2 0x00003000
- #define _VO2L_CTL_ALPOUT 0x0003c000
-
- /*
- * _VO2L_CTL_REG3 shift defines.
- */
- #define _VO2L_CTL_SHIFT_CP_CTL 0x3
- #define _VO2L_CTL_SHIFT_CP_BRD_ID 0x8
- #define _VO2L_CTL_SHIFT_GPI_CNTL_CH1 0xa
- #define _VO2L_CTL_SHIFT_GPI_CNTL_CH2 0xc
- #define _VO2L_CTL_SHIFT_ALPOUT 0xe
-
- /*
- * _VO2L_CTL_REG3_CP_CTL value defines... These values are pre-shifted.
- */
- #define _VO2L_CP_RGBA_12_PIX 0x0
- #define _VO2L_CP_RGB_5_TEX 0x8
- #define _VO2L_CP_RGBA_4_TEX 0x10
- #define _VO2L_CP_RGBA_8_TEX 0x18
- #define _VO2L_CP_FRAME_MODE 0x0
- #define _VO2L_CP_FIELD_MODE 0x80
-
- /*
- * Input clock select values
- */
- #define _VO2L_IN_CLKSEL_VME 0x0
- #define _VO2L_IN_CLKSEL_D1_1 0x1
- #define _VO2L_IN_CLKSEL_D1_2 0x2
- #define _VO2L_IN_CLKSEL_GENIN 0x3
- #define _VO2L_IN_CLKSEL_GENOUT_2X 0x4
- #define _VO2L_IN_CLKSEL_DECODER 0x5
- #define _VO2L_IN_CLKSEL_GFX 0x6
-
- /*
- * _VO2L_ANLG_CTL_REG register bit map definitions
- */
- #define _VO2L_ANLG_IN_GEN_SYNC_0 0x00001
- #define _VO2L_ANLG_IN_GEN_SYNC_1 0x00002
- #define _VO2L_ANLG_IN_GEN_SYNC_2 0x00004
- #define _VO2L_ANLG_SYNC_300MV_EN 0x00008 /* genlock sync select */
- #define _VO2L_ANLG_GEN_300MV_EN 0x00010 /* genlock sync select values */
- #define _VO2L_ANLG_SYNC_OUT_300_EN 0x00020 /* this enables the output sync in the BOB*/
- #define _VO2L_ANLG_GENIN_SEL 0x00040
- #define _VO2L_ANLG_AD_UNUSED 0x00080
- #define _VO2L_ANLG_OUT_GEN_SYNC_0 0x00100
- #define _VO2L_ANLG_OUT_GEN_SYNC_1 0x00200
- #define _VO2L_ANLG_OUT_GEN_SYNC_2 0x00400
- #define _VO2L_ANLG_UV_MODE 0x00800
- #define _VO2L_ANLG_UV_MODE_YGA 0x01000
- #define _VO2L_ANLG_SET_VLAN_CLK_0 0x04000
- #define _VO2L_ANLG_SET_VLAN_CLK_1 0x02000
- #define _VO2L_ANLG_SEL_OUT_CLK_2 0x08000
- #define _VO2L_ANLG_SEL_OUT_CLK_1 0x10000
- #define _VO2L_ANLG_SEL_OUT_CLK_0 0x20000
- #define _VO2L_ANLG_SEL_VOF_CLK_1 0x40000
- #define _VO2L_ANLG_SEL_VOF_CLK_0 0x80000
-
- /*
- * _VO2L_ANLG_CTL_REG mask definitons
- */
- #define _VO2L_ANLG_IN_GEN_SYNC 0x00007
- #define _VO2L_ANLG_OUT_GEN_SYNC 0x00700
- #define _VO2L_ANLG_SET_FIELD 0x06000
- #define _VO2L_ANLG_SEL_OUT_CLK 0x38000
- #define _VO2L_ANLG_SEL_VOF_CLK 0xc0000
-
- /*
- * _VO2L_ANLG_IN_GEN_SYNC values. Thse values are preshifted.
- */
- #define _VO2L_ANLG_IN_GEN_SYNC_300MV 0x0
- #define _VO2L_ANLG_IN_GEN_SYNC_4V 0x1
- #define _VO2L_ANLG_IN_SYNC_GREEN 0x2
- #define _VO2L_ANLG_IN_SYNC_300MV 0x3
- #define _VO2L_ANLG_IN_SYNC_4V 0x4
- #define _VO2L_ANLG_IN_SYNC_COMP 0x5
- #define _VO2L_ANLG_IN_SYNC_YC 0x6
- #define _VO2L_ANLG_IN_GEN_SYNC_GND 0x7
-
- /*
- * _VO2L_ANLG_OUT_GEN_SYNC values. Thse values are preshifted.
- */
- #define _VO2L_ANLG_OUT_GEN_SYNC_300MV 0x000 /*300 mv genlock sync */
- #define _VO2L_ANLG_OUT_GEN_SYNC_4V 0x100 /* 4V genlock sync */
- #define _VO2L_ANLG_OUT_SYNC_GREEN 0x200 /* Sync On Green */
- #define _VO2L_ANLG_OUT_SYNC_300MV 0x300 /* Sync 300mv */
- #define _VO2L_ANLG_OUT_SYNC_4V 0x400 /* SYNC 4V */
- #define _VO2L_ANLG_OUT_SYNC_COMP 0x500 /* Composite In */
- #define _VO2L_ANLG_OUT_SYNC_YC 0x600 /* Y/C IN */
- #define _VO2L_ANLG_OUT_SYNC_STND_ALN 0x700 /* standalone */
- /*
- * _VO2L_ANLG_SEL_OUT_CLK Value defines. These values are pre shifted and pre
- * swizzled.
- */
- #define _VO2L_ANLG_OUT_CLK_VME 0x00000
- #define _VO2L_ANLG_OUT_CLK_D1_2 0x08000
- #define _VO2L_ANLG_OUT_CLK_COMPOSITE 0x10000
- #define _VO2L_ANLG_OUT_CLK_GENOUT 0x20000
- #define _VO2L_ANLG_OUT_CLK_D1_1 0x30000
-
- /*
- * _VO2L_ANLG_SEL_VOF_CLK value defines. These values are pre shifted and pre
- * swizzled.
- */
- #define _VO2L_ANLG_VOF_CLK_GENOUT 0x00000
- #define _VO2L_ANLG_VOF_CLK_D1_1 0x40000
- #define _VO2L_ANLG_VOF_CLK_COMPOSITE 0x80000
- #define _VO2L_ANLG_VOF_CLK_D1_2 0xc0000
-
- #define _VO2L_ACTL_UNUSED 0x00000001
-
- /*
- * _VO2L_STATUS
- */
- #define _VO2L_STAT_UNUSED_0 0x00000001
- #define _VO2L_STAT_UNUSED_1 0x00000002
- #define _VO2L_STAT_UNUSED_2 0x00000004
- #define _VO2L_STAT_ENC_GEN_SYNC_VALID 0x00000008
- #define _VO2L_STAT_ENC_INT_L 0x00000010
- #define _VO2L_STAT_FBA_VID_BC_DONEP 0x00000020
- #define _VO2L_STAT_FBA_ALP_DONEP 0x00000040
- #define _VO2L_STAT_FBB_BC_DONEP 0x00000080
- #define _VO2L_STAT_CP_DONEP 0x00000100
- #define _VO2L_STAT_CKG_DONEP 0x00000200
- #define _VO2L_STAT_FBA_CRX_DONEP 0x00000400
- #define _VO2L_STAT_FBB_CRX_DONEP 0x00000800
- #define _VO2L_STAT_D1_CH1_DONEP 0x00001000
- #define _VO2L_STAT_D1_CH2_DONEP 0x00002000
- #define _VO2L_STAT_D1_OUT_DONEP 0x00004000
- #define _VO2L_STAT_GENIN_DONEP 0x00008000
- #define _VO2L_STAT_GENOUT_DONEP 0x00010000
- #define _VO2L_STAT_PACTL_DONEP 0x00020000
- #define _VO2L_STAT_VDR_DONEP 0x00040000
- #define _VO2L_STAT_VOF_DONEP 0x00080000
-
- /*
- * _VO2L_VOF
- */
- #define _VO2L_VOF_CNTRL (_VO2L_VOF+0)
- #define _VO2L_VOF_VERT_SEQ_COUNTER (_VO2L_VOF+1)
- #define _VO2L_VOF_LINE_TYPE_LUT (_VO2L_VOF+2)
- #define _VO2L_VOF_LINE_LENGTH_LOW (_VO2L_VOF+3)
- #define _VO2L_VOF_LINE_LENGTH_HIGH (_VO2L_VOF+4)
- #define _VO2L_VOF_LINE_DURATION (_VO2L_VOF+5)
- #define _VO2L_VOF_EDGE_MEMORY_ADDR (_VO2L_VOF+6)
- #define _VO2L_VOF_EDGE_MEMORY_DATA (_VO2L_VOF+7)
-
- /* VOF_CNTRL REGISTER value defines */
- #define _VO2L_VOF_CNTRL_RUNSTOP 0x00000001
- #define _VO2L_VOF_CNTRL_RUN 0x00000000
- #define _VO2L_VOF_CNTRL_STOP 0x00000001
- #define _VO2L_VOF_CNTRL_SETUPSYNC_0 0x00000002
- #define _VO2L_VOF_CNTRL_TTLVIDLEV 0x00000004
- #define _VO2L_VOF_CNTRL_TTLLEV 0x00000000
- #define _VO2L_VOF_CNTRL_VIDLEV 0x00000004
- /*
- * Bits 3 and 4 of the vof control register used to select delay values for
- * analog 525, analog 625, and digital, but they were unused, because the VOF
- * always set the clock delays to two for all formats (thus the bit setting
- * didn't matter). These bits have now been redefined:
- *
- * Bit 3 of the [7..0] numbered vof control register is now the analog
- * blanking enable; when set, we will blank the video signal for the duration
- * of the frame. When clear, normal vertical/horizontal blanking ensues.
- * This bit is provided so that users may turn off the incorrectly timed
- * "monitor" signal when running digital output formats.
- *
- * Bit 4 is unused, and available for future expansion.
- */
- #define _VO2L_VOF_CNTRL_ANALOG_BLANK_EN 0x00000008
- #define _VO2L_VOF_CNTRL_UNUSED_BIT4 0x00000010
-
- #define _VO2L_VOF_CNTRL_LOCKMODE 0x00000020
- #define _VO2L_VOF_CNTRL_BURSTLOCK 0x00000020
- #define _VO2L_VOF_CNTRL_NONBURSTLOCK 0x00000000
- #define _VO2L_VOF_CNTRL_EDGEMEM 0x00000040
- #define _VO2L_VOF_CNTRL_EDGEMEM_LOW 0x00000000
- #define _VO2L_VOF_CNTRL_EDGEMEM_HIGH 0x00000040
- #define _VO2L_VOF_CNTRL_SETUPSYNC_1 0x00000080
- #define _VO2L_VOF_CNTRL_SETUPSYNC 0x00000082
-
- #define _VO2L_VOF_CNTRL_SETUPSYNC_M0 0x00000000
- #define _VO2L_VOF_CNTRL_SETUPSYNC_M1 0x00000002
- #define _VO2L_VOF_CNTRL_SETUPSYNC_M2 0x00000080
- #define _VO2L_VOF_CNTRL_SETUPSYNC_M3 0x00000082
-
-
- /*
- * Digital pots (analog calibration)
- */
- #define _VO2_DPOT_OFF_AD_G_Y 1
- #define _VO2_DPOT_GAIN_AD_G_Y 2
- #define _VO2_DPOT_OFF_AD_B_U 3
- #define _VO2_DPOT_GAIN_AD_B_U 4
- #define _VO2_DPOT_OFF_AD_R_V 5
- #define _VO2_DPOT_GAIN_AD_R_V 6
- #define _VO2_DPOT_OFF_AD_ALP 7
- #define _VO2_DPOT_GAIN_AD_ALP 8
- #define _VO2_DPOT_GAIN_DA_G_Y 9
- #define _VO2_DPOT_GAIN_DA_B_U 10
- #define _VO2_DPOT_GAIN_DA_R_V 11
- #define _VO2_DPOT_GAIN_DA_ALP 12
- #define _VO2_DPOT_CLK_REF_FINE_P 13
- #define _VO2_DPOT_UNUSED_1 14
- #define _VO2_DPOT_UNUSED_2 15
- #define _VO2_DPOT_UNUSED_3 16
-
- /*
- * _VO2L_GENOUT_R2 register bit definitons.
- */
- #define _VO2L_GENOUT_LINE_DELAY_HI 0x03
- #define _VO2L_GENOUT_PAL_SELECT 0x04
- #define _VO2L_GENOUT_D1_FLD_SEL 0x08
- #define _VO2L_GENOUT_VOF_RESET_DIS 0x10
- #define _VO2L_GENOUT_STND_ALN_DIS 0x20
- #define _VO2L_GENOUT_COMP_IN_CLK_SEL 0xc0
-
- /*
- * _VO2L_GENOUT_R3 register bit definitons.
- */
- #define _VO2L_GENOUT_LINE_DELAY_LO 0xff
-
- /* _VO2L_ENC registers */
- #define _VO2L_ENC_CNTL_REG 0x00
- #define _VO2L_ENC_FMT_REG 0x01
- #define _VO2L_ENC_INTFC_REG 0x02
- #define _VO2L_ENC_TEST_REG 0x03
- #define _VO2L_ENC_KEY_REG 0x04
-
- #define _VO2L_ENC_SY_REG 0x10
- #define _VO2L_ENC_BR_REG 0x11
- #define _VO2L_ENC_BU_REG 0x12
- #define _VO2L_ENC_CBP_REG 0x13
- #define _VO2L_ENC_XBP_REG 0x14
- #define _VO2L_ENC_VA_REG 0x15
- #define _VO2L_ENC_VB_REG 0x16
- #define _VO2L_ENC_VC_REG 0x17
- #define _VO2L_ENC_MSB_REG 0x18
-
- #define _VO2L_ENC_FP_REG 0x19
- #define _VO2L_ENC_EL_REG 0x1a
- #define _VO2L_ENC_EH_REG 0x1b
- #define _VO2L_ENC_SL_REG 0x1c
- #define _VO2L_ENC_SH_REG 0x1d
- #define _VO2L_ENC_CBL_REG 0x1e
-
- #define _VO2L_ENC_FREQL_REG 0x20
- #define _VO2L_ENC_FREQL3_REG 0x21
- #define _VO2L_ENC_FREQL2_REG 0x22
- #define _VO2L_ENC_FREQLM_REG 0x23
-
-
- #define _VO2L_ENC_SYSPHL_REG 0x24
- #define _VO2L_ENC_SYSPHM_REG 0x25
- #define _VO2L_ENC_BURPHL_REG 0x26
- #define _VO2L_ENC_BURPHM_REG 0x27
-
- /*
- *
- */
- #define _VO2_ENC_GEN_HPHASE_MASK 0x1fff000
- #define _VO2_ENC_GEN_HPHASE_SHIFT 12
-
- /*
- * DECODER register map
- */
- #define _VO2L_DEC_CR0_REG 0x00
- #define _VO2L_DEC_CR1_REG 0x01
- #define _VO2L_DEC_CR2_REG 0x02
- #define _VO2L_DEC_CR3_REG 0x03
- #define _VO2L_DEC_CR4_REG 0x04
- #define _VO2L_DEC_CR5_REG 0x05
- #define _VO2L_DEC_CR6_REG 0x06
- #define _VO2L_DEC_CR7_REG 0x07
- #define _VO2L_DEC_BRIGHT_REG 0x08
- #define _VO2L_DEC_CONT_REG 0x09
- #define _VO2L_DEC_SAT_REG 0x0a
- #define _VO2L_DEC_HUE_REG 0x0b
- #define _VO2L_DEC_HCLK_LO_REG 0x0c
- #define _VO2L_DEC_HCLK_HI_REG 0x0d
- #define _VO2L_DEC_HDLY_LO_REG 0x0e
- #define _VO2L_DEC_HDLY_HI_REG 0x0f
- #define _VO2L_DEC_PIX_LO_REG 0x10
- #define _VO2L_DEC_PIX_HI_REG 0x11
- #define _VO2L_DEC_VDLY_LO_REG 0x12
- #define _VO2L_DEC_VDLY_HI_REG 0x13
- #define _VO2L_DEC_LINES_LO_REG 0x14
- #define _VO2L_DEC_LINES_HI_REG 0x15
- #define _VO2L_DEC_P0_REG 0x16
- #define _VO2L_DEC_P1_REG 0x17
- #define _VO2L_DEC_P2_REG 0x18
- #define _VO2L_DEC_AGC_REG 0x19
- #define _VO2L_DEC_BURST_REG 0x1a
- #define _VO2L_DEC_SAMP_LO_REG 0x1b
- #define _VO2L_DEC_SAMP_HI_REG 0x1c
- #define _VO2L_DEC_POLARITY_REG 0x1d
- #define _VO2L_DEC_SW_RESET 0xff
-
-
- /*
- * Lookup table sizes
- */
- #define _VO2_DIGITAL_LUT_SIZE 4096
- #define _VO2_ANALOG_LUT_SIZE 4096
- #define _VO2_PA_LUT_SIZE 1024
- #define _VO2_ENC_LUT_SIZE 256 /* encoder LUT size */
-
- #if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
-
- /*
- * Stuff returned to user on a GETBOARDINFO call
- * Anything in here is public knowledge
- */
- struct vo2_info {
- struct vid_info vid_info;
- int bdrev;
- int hascpi;
- int hasdgi;
- int hasbob;
- int hassd1;
- int gfxpipe;
- int pabrev;
- };
-
- /*
- * Our private one-per-board data structure
- * The user can't get at any of this
- */
- struct vo2_data {
- struct vid_data vid_data;
- struct vo2_info info;
-
- int vmebus;
- int boardnum;
- void *baseaddr;
- unsigned int intmode;
-
- struct proc * user_proc;
-
- /*
- * A strict lock for VME-bus FIFO reads and writes.
- * Also used for localaddr/localdata register.
- */
- lock_t vmecmd_lock;
-
- /*
- * A strict lock for the shadowing stuff.
- */
- lock_t shadow_lock;
-
- #define VO2_SEMA_DMA_0 0
- #define VO2_SEMA_DMA_1 1
- #define VO2_SEMA_MISC 2
- #define VO2_SEMA_VLIST 3
- #define VO2_SEMA_VLAN 4
- #define VO2_TIMEOUT_VLIST 5
-
- sema_t dma_int_sema[4]; /* sleep semaphores */
- toid_t dma_timeout[5];
-
- dmamap_t *dmamap[4]; /* DMA maps */
- /*
- * maximum size of video DMA (entries 0 and 1): 768 x 576 x 4 / 4096 = 432
- * maximum size of general-purpose DMA (entry 2): 16Kbytes = 4 pages
- * maximum size of vlist DMA (entry 3): 20Kbytes = 5 pages
- */
- #define VO2_VIDEO_DMA_BUFFER_PAGES 432
- #define VO2_GP_DMA_BUFFER_PAGES 4
- #define VO2_VLIST_DMA_BUFFER_PAGES 5
- int npages[4]; /* size of DMA maps */
-
- #ifndef USE_K2_SPACE
- int actpages;
- unsigned int *pagelist[2];
- void *kvaddr[2]; /* k2 addr */
- #endif /* USE_K2_SPACE */
-
- sema_t dma_video_sema;
- unsigned int *dma_video_kbuf[2]; /* non-Onyx only */
- unsigned char *dma_video_mapaddr[2]; /* non-Onyx only */
-
- sema_t dma_misc_sema;
- unsigned int *dma_misc_kbuf;
- unsigned char *dma_misc_mapaddr;
-
- lock_t vlist_lock;
- sema_t vlist_sema;
- unsigned int *dma_vlist_kbuf;
- unsigned int *dma_vlist_dmabuf;
- unsigned char *dma_vlist_mapaddr;
- unsigned int vlist_n;
- unsigned int vlist_max;
- unsigned int vlist_hiwater;
- unsigned int vlist_enable;
- unsigned int vlist_ticks;
- toid_t vlist_timeout;
-
- unsigned int dmrb_inuse;
- unsigned int dmrb_key; /* passed by user */
- int dmrb_aid; /* attach id */
- unsigned int dmrb_nfields;
- unsigned int dmrb_fieldsize;
- int dmrb_buffer;
-
- int dma_abort;
- int dma_trigger;
- int dma_xferStartNotify;
- int dma_xferStopNotify;
-
- sema_t dmrb_callback_sema;
-
- sema_t gpi_1_sema;
- sema_t gpi_2_sema;
- sema_t vlan_sema;
-
- struct pollhead *ph;
- lock_t events_lock;
- unsigned int vo2eventmask;
- unsigned int vo2events;
-
- /*
- * The vlan_watchdog variable is normally zero, but gets set to
- * one by the vlan timeout routine, so that a spinning kernel
- * process can take appropriate action.
- */
- int vlan_watchdog;
-
-
- #define _VO2_H_NONE 0
- #define _VO2_H_VME_CNTRL 1
- #define _VO2_H_VME_INT_MASK 2
- #define _VO2_H_CTL_REG1 3
- #define _VO2_H_CTL_REG2 4
- #define _VO2_H_CTL_REG3 5
- #define _VO2_H_CTL_ANLG 6
- #define _VO2_H_VOF_CNTRL 7
-
- #define _VO2_H_PA_MODE_R 8
- #define _VO2_H_PA_MODE_G 9
- #define _VO2_H_PA_MODE_B 10
- #define _VO2_H_PA_MODE_A 11
- #define _VO2_H_PA_ABMODE_R 12
- #define _VO2_H_PA_ABMODE_G 13
- #define _VO2_H_PA_ABMODE_B 14
- #define _VO2_H_PA_ABMODE_A 15
- #define _VO2_H_PA_DRMODE_R 16
- #define _VO2_H_PA_DRMODE_G 17
- #define _VO2_H_PA_DRMODE_B 18
- #define _VO2_H_PA_DRMODE_A 19
-
- #define _VO2_H_AP_MODE_R 20
- #define _VO2_H_AP_MODE_G 21
- #define _VO2_H_AP_MODE_B 22
- #define _VO2_H_AP_MODE_A 23
- #define _VO2_H_AP_ABMODE_R 24
- #define _VO2_H_AP_ABMODE_G 25
- #define _VO2_H_AP_ABMODE_B 26
- #define _VO2_H_AP_ABMODE_A 27
- #define _VO2_H_AP_DRMODE_R 28
- #define _VO2_H_AP_DRMODE_G 29
- #define _VO2_H_AP_DRMODE_B 30
- #define _VO2_H_AP_DRMODE_A 31
-
- #define _VO2_H_DR_MODE_R 32
- #define _VO2_H_DR_MODE_G 33
- #define _VO2_H_DR_MODE_B 34
- #define _VO2_H_DR_MODE_A 35
- #define _VO2_H_DR_ABMODE_R 36
- #define _VO2_H_DR_ABMODE_G 37
- #define _VO2_H_DR_ABMODE_B 38
- #define _VO2_H_DR_ABMODE_A 39
- #define _VO2_H_DR_DRMODE_R 40
- #define _VO2_H_DR_DRMODE_G 41
- #define _VO2_H_DR_DRMODE_B 42
- #define _VO2_H_DR_DRMODE_A 43
-
- #define _VO2_H_FBA_SRC_DST 44
- #define _VO2_H_FBB_SRC_DST 45
- #define _VO2_H_FBA_A_SRC_DST 46
-
- #define _VO2_H_PACTL_MODE 47
-
- #define _VO2_H_FBA_COMMAND 48
- #define _VO2_H_FBB_COMMAND 49
- #define _VO2_H_FBA_ALPHA_COMMAND 50
-
- #define _VO2_H_FBA_CLK_PLL_CTL_REG1 51
- #define _VO2_H_FBB_CLK_PLL_CTL_REG1 52
- #define _VO2_H_FBA_ALPHA_CLK_PLL_CTL_REG1 53
- #define _VO2_H_GENOUT_R2 54
- #define _VO2_H_GENOUT_R3 55
- #define _VO2_H_D1_1 56
- #define _VO2_H_D1_2 57
- #define _VO2_H_FBA_CLK_PLL_CTL_REG2 58
- #define _VO2_H_FBB_CLK_PLL_CTL_REG2 59
- #define _VO2_H_FBA_ALPHA_CLK_PLL_CTL_REG2 60
-
- /* the following are software-only shadows */
- #define _VO2_H_DONE_VIDINIT 100
- #define _VO2_H_FBA_FILTER_DELAY 101
- #define _VO2_H_FBB_FILTER_DELAY 102
- #define _VO2_H_FBA_COARSE_PHASE_X 103
- #define _VO2_H_FBB_COARSE_PHASE_X 104
- #define _VO2_H_FBA_ALPHA_CHROMA_DELAY 105
- #define _VO2_H_FBB_ALPHA_CHROMA_DELAY 106
- #define _VO2_H_FBA_ALPHA_COARSE_PHASE_X 107
- #define _VO2_H_FBB_ALPHA_COARSE_PHASE_X 108
- #define _VO2_H_FBA_INPUT_SOURCE 109
- #define _VO2_H_FBA_ALPHA_INPUT_SOURCE 110
- #define _VO2_H_FBB_INPUT_SOURCE 111
- #define _VO2_H_FBA_OUT_AP_DELAY 112
- #define _VO2_H_FBB_OUT_AP_DELAY 113
- #define _VO2_H_FBA_ALPHA_OUT_AP_DELAY 114
- #define _VO2_H_DIG_OUT_MATRIX_DELAY 115
- #define _VO2_H_ANLG_OUT_MATRIX_DELAY 116
- #define _VO2_H_OUTPUT_FILTER_DELAY 117
- #define _VO2_H_VID_OUT_ANALOG 118
- #define _VO2_H_CURRENT_VOF 119
- #define _VO2_H_FBA_TIMING 120
- #define _VO2_H_FBA_ALPHA_TIMING 121
- #define _VO2_H_FBB_TIMING 122
- #define _VO2_H_VDR_OFFSETS 123
- #define _VO2_H_VDR_INPATH_PACKING 124
- #define _VO2_H_VDR_OUTPATH_PACKING 125
- #define _VO2_H_GENIN_SRC 126
- #define _VO2_H_GENOUT_SRC 127
- #define _VO2_H_BURST_LOCK 128
- #define _VO2_H_SYNC_LEVEL 129
- #define _VO2_H_GENSYNC_LEVEL 130
- #define _VO2_H_OUTPUT_BLANK 131
- #define _VO2_H_OUTPUT_4444 132
- #define _VO2_H_OUTPUT_DELAY 133
- #define _VO2_H_GENLOCK_CHIP_MSB 134
- #define _VO2_H_GENLOCK_CHIP_LSB 135
- #define _VO2_H_OUTPUT_HPHASE 136
- #define _VO2_H_OUT_CLK_SRC 137
- #define _VO2_H_ANALOG_OUT_CS 138
- #define _VO2_H_VDR_INPATH_XFERFRAMES 139
- #define _VO2_H_VDR_OUTPATH_XFERFRAMES 140
- #define _VO2_H_ANALOG_IN_COMPOSITE 141
- #define _VO2_H_VID_OUT_TIMING 142
- #define _VO2_H_FBA_FIELD_DOMINANCE 143
-
- #define _VO2_H_MAXSHADOW 150
- unsigned int shadow[_VO2_H_MAXSHADOW + 1];
- unsigned int seqNo;
- unsigned int media_offset;
- unsigned int image_offset;
- unsigned int fieldwidth;
- unsigned int fieldheight;
- struct timeval lasttime;
- };
-
- #endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
-
- /*
- * Device driver IOCTLs
- */
- #define VO2_GET_VERSION (VID_PRIVATE_BASE + 0)
- #define VO2_GET_BOARD_INFO (VID_PRIVATE_BASE + 1)
- #define VO2_W_VME (VID_PRIVATE_BASE + 2)
- #define VO2_S_VME (VID_PRIVATE_BASE + 3)
- #define VO2_R_VME (VID_PRIVATE_BASE + 4)
- #define VO2_D_VME (VID_PRIVATE_BASE + 5)
- #define VO2_W_LOC (VID_PRIVATE_BASE + 6)
- #define VO2_S_LOC (VID_PRIVATE_BASE + 7)
- #define VO2_R_LOC (VID_PRIVATE_BASE + 8)
- #define VO2_D_LOC (VID_PRIVATE_BASE + 9)
- #define VO2_W_LIND (VID_PRIVATE_BASE + 10)
- #define VO2_S_LIND (VID_PRIVATE_BASE + 11)
- #define VO2_R_LIND (VID_PRIVATE_BASE + 12)
- #define VO2_D_LIND (VID_PRIVATE_BASE + 13)
- #define VO2_W_N_LOC (VID_PRIVATE_BASE + 14)
- #define VO2_R_N_LOC (VID_PRIVATE_BASE + 15)
- #define VO2_D_N_LOC (VID_PRIVATE_BASE + 16)
- #define VO2_W_N_LIND (VID_PRIVATE_BASE + 17)
- #define VO2_R_N_LIND (VID_PRIVATE_BASE + 18)
- #define VO2_D_N_LIND (VID_PRIVATE_BASE + 19)
- #define VO2_SET_SHADOW (VID_PRIVATE_BASE + 20)
- #define VO2_GET_SHADOW (VID_PRIVATE_BASE + 21)
- #define VO2_SET_N_SHADOW (VID_PRIVATE_BASE + 22)
- #define VO2_GET_N_SHADOW (VID_PRIVATE_BASE + 23)
- #define VO2_W_XILINX (VID_PRIVATE_BASE + 24)
- #define VO2_W_VOF (VID_PRIVATE_BASE + 25)
- #define VO2_W_DMA (VID_PRIVATE_BASE + 26)
- #define VO2_R_DMA (VID_PRIVATE_BASE + 27)
- #define VO2_W_DMAVID (VID_PRIVATE_BASE + 28)
- #define VO2_R_DMAVID (VID_PRIVATE_BASE + 29)
- #define VO2_W_EEPROM (VID_PRIVATE_BASE + 30)
- #define VO2_R_EEPROM (VID_PRIVATE_BASE + 31)
- #define VO2_SLEEP_TRIGGER (VID_PRIVATE_BASE + 32)
- #define VO2_DMRB_ATTACH (VID_PRIVATE_BASE + 33)
- #define VO2_DMRB_DETACH (VID_PRIVATE_BASE + 34)
- #define VO2_DMRB_READ (VID_PRIVATE_BASE + 35)
- #define VO2_DMRB_WRITE (VID_PRIVATE_BASE + 36)
- #define VO2_DMA_ABORT (VID_PRIVATE_BASE + 37)
- #define VO2_DMA_TRIGGER (VID_PRIVATE_BASE + 38)
- #define VO2_DMA_NOTIFY (VID_PRIVATE_BASE + 39)
- #define VO2_GET_EVENTS (VID_PRIVATE_BASE + 40)
- #define VO2_SET_EVENTMASK (VID_PRIVATE_BASE + 41)
- #define VO2_VLAN_DOWNLOAD (VID_PRIVATE_BASE + 42)
- #define VO2_VLAN_READ_BYTE (VID_PRIVATE_BASE + 43)
- #define VO2_VLAN_WRITE_BYTE (VID_PRIVATE_BASE + 44)
- #define VO2_STOPSTART_VLIST (VID_PRIVATE_BASE + 45)
-
- #if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
-
- /*
- * Structure for writing/reading a register
- */
- struct vo2_rw_reg {
- void *addr; /* base address (VME or local), for all */
- void *adata; /* address of data, for indirect fncs only */
- void *indaddr; /* indirect address, for indirect fncs only */
- unsigned int mask; /* mask, for set-bit fncs only */
- unsigned int val; /* value, for single location fncs only */
- unsigned int *data; /* pointer to data, for block fncs only */
- int n; /* number of items, for block fncs only */
- };
-
- /*
- * Structure for programming a xilinx
- */
- struct vo2_w_xilinx {
- int which;
- int nbytes;
- int nbits;
- int nframes;
- int bitsperframe;
- unsigned char *data;
- };
-
- /*
- * Structure for programming a vof
- */
- struct vo2_w_vof {
- unsigned char *topdata;
- int topcnt;
- unsigned char *bodydata;
- int bodycnt;
- };
-
- /*
- * Structure for doing a DMA
- */
- struct vo2_dma {
- unsigned char *memaddr; /* IRIX memory address (virtual user space) */
- unsigned char *brdaddr; /* vo2 board localbus address for normal xfer */
- unsigned int len; /* #words; or #fields for a video transfer */
- unsigned int fieldsize; /* #words/field for a video transfer */
- unsigned int buffer; /* buffer on VO2: A-RGB, A-ALPHA, or B */
- unsigned int xferframes; /* transfer frames (default is fields) */
- };
-
- /*
- * struct vo2_dmrb_args is the arg for the VO2_DMRB_ ioctls.
- */
- struct vo2_dmrb_args {
- unsigned int dataDirection; /* 0 -> (vid to mem), 1 -> (mem to vid) */
- unsigned int key; /* dmrb key from user */
- unsigned int len; /* #fields for a video transfer */
- unsigned int fieldsize; /* #words/field for a video transfer */
- unsigned int fieldwidth; /* width of the field */
- unsigned int fieldheight; /* height of the field */
- unsigned int buffer; /* buffer on VO2: A-RGB, A-ALPHA, or B */
- unsigned int xferframes; /* transfer frames (default is fields) */
- unsigned int media_offset; /* media offset in the info structure */
- unsigned int image_offset; /* image offset in the info structure */
- };
-
- /* for dataDirection */
- #define VO2_VID_TO_MEM 0
- #define VO2_MEM_TO_VID 1
-
- /* for buffer */
- #define VO2_BUF_A_RGB 1
- #define VO2_BUF_A_ALPHA 2
- #define VO2_BUF_A_RGBA 3
- #define VO2_BUF_B_RGBA 4
-
- /*
- * Structure which contains an integer value; we either take the least
- * significant byte and write it to the VLAN, or return a byte read from
- * the VLAN in the least significant byte. If an error occurred during the
- * read, we will return EFAULT and set the byte equal to the return value
- * (0xffffff00).
- */
- struct vo2_rw_vlan {
- int data;
- };
-
- #define VO2_VLAN_READBACK_AND_VERIFY 0x1
- #define VO2_VLAN_ISSUE_GO_COMMAND 0x2
-
- /*
- * Structure which contains the VLAN code to be downloaded.
- * Supply one or more flags to control the behavior of the downloaded code.
- *
- * For diags, we may want to download close to 32K worth of memory test data
- * which can be read back by the prom with the VO2_VLAN_READBACK_AND_VERIFY
- * flag, but which should NOT executed as Z-80 code (i.e. don't provide the
- * VO2_VLAN_ISSUE_GO_COMMAND flag). We cannot download a full 32K worth of
- * data because a small amount of stack memory is needed by the Z-80 processor
- * at the top of SRAM (e.g. reserve maybe 200 bytes for Z-80 stack).
- */
- struct vo2_w_vlan {
- unsigned char *data;
- int size;
- int flags;
- };
-
- /*
- * Structure which specifies which GPI outputs should map to the notify
- * events which could get issued at the start and finish of each dma transfer.
- */
- struct vo2_dma_notify_args {
- int xferStartChannel;
- int xferStopChannel;
- };
-
- /*
- * Structure of the eeprom
- */
- #define VO2_EEPROM_SIZE 8192
- #define VO2_EEPROM_HEADER_SIZE 16
- #define VO2_EEPROM_ID 0x564F32
- #define VO2_EEPROM_REV 0x1
-
- struct calib_entry {
- unsigned char in_green_y_offset;
- unsigned char in_green_y_gain;
- unsigned char in_blue_u_offset;
- unsigned char in_blue_u_gain;
- unsigned char in_red_v_offset;
- unsigned char in_red_v_gain;
- unsigned char in_alpha_offset;
- unsigned char in_alpha_gain;
- unsigned char out_green_y_gain;
- unsigned char out_blue_u_gain;
- unsigned char out_red_v_gain;
- unsigned char out_alpha_gain;
- };
-
- #define _VO2_CALIB_FORMAT_RGB_WITH_SETUP 0
- #define _VO2_CALIB_FORMAT_RGB_WITHOUT_SETUP 1
- #define _VO2_CALIB_FORMAT_BETACAM 2
- #define _VO2_CALIB_FORMAT_MII 3
- #define _VO2_CALIB_FORMAT_SMPTE_YUV 4
- #define _VO2_CALIB_FORMAT_N 5
-
- #define _VO2_CALIB_TIMING_525 0
- #define _VO2_CALIB_TIMING_625 1
- #define _VO2_CALIB_TIMING_N 2
-
- struct vo2_eeprom {
- unsigned int prom_id;
- unsigned int prom_length;
- unsigned int prom_checksum;
- unsigned int prom_revision;
-
- /*
- * Diags section. Diags may always R/W this area. This area is not
- * included in the checksum calculations.
- */
- char diags_area[16];
-
- /*
- * Serial number section. Writable only by SGI. Should never be changed.
- */
- time_t t_serial_no; /* time serial number recorded */
- char serial_no[8]; /* serial number */
- char serial_filler[980]; /* fill first 1024 bytes */
-
- /*
- * Factory calibration section. Writable only by SGI. Not used by
- * software other than to copy to user settings.
- */
- time_t t_factory_calib; /* time of factory calibration */
- struct calib_entry factory_gain[_VO2_CALIB_FORMAT_N][_VO2_CALIB_TIMING_N];
- unsigned char factory_fineclock[_VO2_CALIB_TIMING_N];
- char factory_filler[898]; /* fill 1024 bytes */
-
- /*
- * User calibration section. Writeable by user. ONLY these values
- * should be used by software.
- */
- time_t t_user_calib; /* time of user calibration */
- struct calib_entry user_gain[_VO2_CALIB_FORMAT_N][_VO2_CALIB_TIMING_N];
- unsigned char user_fineclock[_VO2_CALIB_TIMING_N];
- char user_filler[898]; /* fill 1024 bytes */
-
- /*
- * There are 5,120 bytes left.
- * We may wish to store a VOF???
- * Other user defaults? Dirty pictures? Laundry list??
- */
- };
-
- #endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
-
- /*
- * Defines for referring to a particular xilinx
- */
- #define _VO2_XILINX_VLC 0
- #define _VO2_XILINX_BC1 1
- #define _VO2_XILINX_BC2 2
- #define _VO2_XILINX_BC3 3
- #define _VO2_XILINX_CPF 4
- #define _VO2_XILINX_CKG 5
- #define _VO2_XILINX_CRX1 6
- #define _VO2_XILINX_CRX2 7
- #define _VO2_XILINX_D1IN1 8
- #define _VO2_XILINX_D1IN2 9
- #define _VO2_XILINX_D1OUT 10
- #define _VO2_XILINX_GIN 11
- #define _VO2_XILINX_GOUT 12
- #define _VO2_XILINX_PAC 13
- #define _VO2_XILINX_VDR 14
- #define _VO2_XILINX_VOF 15
-
- /*
- * PACTL mode register defines.
- */
- #define _VO2L_PACTL_MODE_FILTER 0x003 /* Filter mode */
- #define _VO2L_PACTL_MODE_CM 0x004 /* Chip mode */
- #define _VO2L_PACTL_MODE_IN 0x008 /* DVI output format*/
- #define _VO2L_PACTL_MODE_FR 0x010 /* Flicker reduction*/
- #define _VO2L_PACTL_MODE_SF 0x020 /* Start field */
- #define _VO2L_PACTL_MODE_FM_LOCK 0x040 /* Top line flag */
- #define _VO2L_PACTL_MODE_FRAME 0x080 /* Frame ready flag */
- #define _VO2L_PACTL_MODE_RESET 0x100 /* Reset 0,1,0 */
- #define _VO2L_PACTL_MODE_WD 0x200 /* write disable */
- #define _VO2L_PACTL_MODE_FD 0x400 /* 1=625,0=525 */
- /*
- * PACTL_INTERLACE value
- */
- #define _VO2_PACTL_HI_INTERLACE 0x01 /* hi res interlace format */
- #define _VO2_PACTL_HI_INTER_SHIFT 0x03
- /*
- * PACTL_LO_XPIXEL_LINE masks .
- */
- #define _VO2L_PACTL_LO_XPIXEL_MASK 0x3ff /* LOw res output pixels */
- #define _VO2L_PACTL_LO_XDEL_MASK 0xc00 /* X delay pixels */
-
- /*
- * PACTL_LO_XPIXEL_LINE Shift value
- */
- #define _VO2L_PACTL_LO_XDEL_SHIFT 0x0a /* values for XDEL values */
-
- /*
- * PACTL_HI_XYCLEAR masks
- */
- #define _VO2L_PACTL_HI_XCLEAR 0x03f
- #define _VO2L_PACTL_HI_YCLEAR 0xfc0
- /*
- * PACTL_HI_XYCLEAR shifts
- */
- #define _VO2L_PACTL_HI_YCLEAR_SHIFT 0x6
-
- /*
- * _VO2L_PACTL_CLOCK_CTL1 register bits.
- */
- #define _VO2L_PACTL_CLOCK_CTL1_1F0 0x003
- #define _VO2L_PACTL_CLOCK_CTL1_1F1 0x00c
- #define _VO2L_PACTL_CLOCK_CTL1_2F0 0x030
- #define _VO2L_PACTL_CLOCK_CTL1_2F1 0x0c0
- #define _VO2L_PACTL_CLOCK_CTL1_3F0 0x300
- #define _VO2L_PACTL_CLOCK_CTL1_3F1 0xc00
-
- /*
- * _VO2L_PACTL_CLOCK_CTL2 register bits.
- */
- #define _VO2L_PACTL_CLOCK_CTL2_4F0 0x003
- #define _VO2L_PACTL_CLOCK_CTL2_4F1 0x00c
- #define _VO2L_PACTL_CLOCK_CTL2_TEST 0x030
- #define _VO2L_PACTL_CLOCK_CTL2_FS 0x0c0
- #define _VO2L_PACTL_CLOCK_CTL2_CLK_SEL 0x300
-
- #define _VO2_PACTL_CLOCK_RATE_LOW 15000000
- #define _VO2_PACTL_CLOCK_RATE_MEDIUM 25000000
- #define _VO2_PACTL_CLOCK_RATE_SYNCH 30000000
-
- #define _VO2_PACTL_CLOCK_SEL_LOW 0x010
- #define _VO2_PACTL_CLOCK_SEL_MEDIUM 0x000
- #define _VO2_PACTL_CLOCK_SEL_HIGH 0x080
-
- #define _VO2L_PACTL_CLOCK_SEL_SYNCH 0x100
-
- /*
- * Defines for the PA registers. Look at PA2 spec for details
- */
- #define _VO2_PA_MODE 0x000
- #define _VO2_PA_ABMODE 0x001
- #define _VO2_PA_DRMODE 0x002
- #define _VO2_PA_APMODE 0x002 /* In AP mode DRMODE becomes APMODE */
- #define _VO2_PA_HOR_COEF_0_1 0x003
- #define _VO2_PA_HOR_COEF_2_3 0x004
- #define _VO2_PA_HOR_COEF_4_5 0x005
- #define _VO2_PA_HOR_COEF_6_7 0x006
- #define _VO2_PA_HOR_COEF_8_9 0x007
- #define _VO2_PA_HOR_COEF_10 0x008
- #define _VO2_PA_NOR_COEF_1x2 0x009
- #define _VO2_PA_NOR_COEF_2x3 0x00a
- #define _VO2_PA_NOR_COEF_8x9 0x00b
- #define _VO2_PA_ZDF_COEF_1A 0x00c
- #define _VO2_PA_ZDF_COEF_2A 0x00d
- #define _VO2_PA_ZDF_COEF_3A 0x00e
- #define _VO2_PA_ZDF_COEF_4A 0x00f
- #define _VO2_PA_ZDF_COEF_5A 0x010
- #define _VO2_PA_ZDF_COEF_1B 0x011
- #define _VO2_PA_ZDF_COEF_2B 0x012
- #define _VO2_PA_ZDF_COEF_3B 0x013
- #define _VO2_PA_ZDF_COEF_4B 0x014
- #define _VO2_PA_ZDF_COEF_5B 0x015
- #define _VO2_PA_ZD_X_COMP 0x016
- #define _VO2_PA_ZD_Y_COMP 0x017
- #define _VO2_PA_ZD_X_CNT 0x018
- #define _VO2_PA_ZD_Y_CNT 0x019
- #define _VO2_PA_ZD_SEED 0x01a
- #define _VO2_PA_LOOKUP_TAB_MASK 0x3ff
- #define _VO2_PA_LOOKUP_TAB_DATA 0x400
-
- /*
- * PA_MODE register Bit map.
- */
- #define _VO2_PA_MODE_FILTER 0x003 /* 3x3,2x2,Passthru filter */
- #define _VO2_PA_MODE_CM 0x004 /* Chip mode bit */
- #define _VO2_PA_MODE_TA 0x008 /* Temporal averaging */
- #define _VO2_PA_MODE_FR 0x010 /* Flicker Reduction */
- #define _VO2_PA_MODE_TM 0x020 /* Test Mode */
- #define _VO2_PA_MODE_BP 0x040 /* PA Bypass */
- #define _VO2_PA_MODE_ZM 0x080 /* Zoom Mode */
- #define _VO2_PA_MODE_XM 0x100 /* Zoom bit for X */
- #define _VO2_PA_MODE_YM 0x200 /* Zoom bit for Y */
- #define _VO2_PA_MODE_FC 0x400 /* Tap filter select */
- #define _VO2_PA_MODE_RM 0x800 /* Rounding Control */
-
- /*
- * PA_ABMODE Register Bit map.
- */
- #define _VO2_PA_ABMODE_CS 0x001 /* Color Sign bit */
- #define _VO2_PA_ABMODE_AP 0x002 /* Alpha Proc mode */
- #define _VO2_PA_ABMODE_OE1 0x004 /* Output enable for port1*/
- #define _VO2_PA_ABMODE_OE2 0x008 /* Output enable for port2*/
-
- /*
- * PA_DRMODE Register Bit map
- */
- #define _VO2_PA_DRMODE_FBA 0x007 /* Output1 mux select */
- #define _VO2_PA_DRMODE_IN1 0x018 /* Input1 mux select */
- #define _VO2_PA_DRMODE_S1 0x020 /* Sign select bit(Out1)*/
- #define _VO2_PA_DRMODE_FBB 0x1c0 /* Output2 mux select */
- #define _VO2_PA_DRMODE_IN2 0x600 /* Input 1 Mux select */
- #define _VO2_PA_DRMODE_S2 0x800 /* Sign select bit(Out2)*/
-
- /*
- * PA_DRMODE value shift defines. For each of the above bit masks
- * these are the shift values that input data should be shifted by.
- */
- #define _VO2_PA_DR_SHIFT_FBA 0x0
- #define _VO2_PA_DR_SHIFT_IN1 0x3
- #define _VO2_PA_DR_SHIFT_S1 0x5
- #define _VO2_PA_DR_SHIFT_FBB 0x6
- #define _VO2_PA_DR_SHIFT_IN2 0x9
- #define _VO2_PA_DR_SHIFT_S2 0xb
-
- /*
- * PA_MODE_FILTER value defines. These values define the scan
- * convert mode
- */
- #define _VO2_PA_FILTER_2x2 0x0 /* 2x2 convolution filter*/
- #define _VO2_PA_FILTER_3x3 0x1 /* 3x3 convolution filter*/
- #define _VO2_PA_FILTER_3_5 0x2 /* 3/5 filter */
- #define _VO2_PA_FILTER_PASS 0x3 /* Pass Thru */
-
-
- /*
- * PA_DRMODE_FBA/FBB value defines . These values define the bus that
- * is connected to output
- */
- #define _VO2_PA_DR_FB_VME 0x0 /* Input 1 */
- #define _VO2_PA_DR_FB_D1_1 0x1 /* Input 2 */
- #define _VO2_PA_DR_FB_D1_2 0x2 /* Input 3 */
- #define _VO2_PA_DR_FB_GFX 0x3 /* Input 4 */
- #define _VO2_PA_DR_FB_LUT 0x5 /* F2/F4 LUT output */
-
- /*
- * PA_DRMODE_IN1 value defines. These values specify the input bus
- * used as the address for F2 look up table.
- */
- #define _VO2_PA_DR_IN1_D1_1_CLK2 0x0 /* Input 2 clocked at CLK2*/
- #define _VO2_PA_DR_IN1_D1_1 0x1 /* Input 2 */
- #define _VO2_PA_DR_IN1_D1_2 0x2 /* Input 3 */
- #define _VO2_PA_DR_IN1_ANALOG 0x3 /* Input 5 */
-
- /*
- * PA_DRMODE_IN2 value defines. These values specify the input bus
- * used as the address for F2 look up table.
- */
- #define _VO2_PA_DR_IN2_D1_2_CLK2 0x0 /* Input 3 clocked at CLK2*/
- #define _VO2_PA_DR_IN2_D1_1 0x1 /* Input 2 */
- #define _VO2_PA_DR_IN2_D1_2 0x2 /* Input 3 */
- #define _VO2_PA_DR_IN2_ANALOG 0x3 /* Input 5 */
-
- /*
- * BUffer controllers (FBA/FBB) SRC_DST select registers bit
- * maps.
- */
- #define _VO2_FB_SRC_SEL 0x07 /* Frame buffer src */
- #define _VO2_FB_DST_SEL 0x18 /* Frame buffer destination*/
-
- /*
- * PA_APMODE registerbit map
- */
- #define _VO2_PA_AP_GFX 0x007 /* Output1 mux select */
- #define _VO2_PA_AP_FBA 0x018 /* Input1 mux select */
- #define _VO2_PA_AP_S1 0x020 /* Sign select bit(Out1)*/
- #define _VO2_PA_AP_VID 0x1c0 /* Output2 mux select */
- #define _VO2_PA_AP_FBB 0x600 /* Input 1 Mux select */
- #define _VO2_PA_AP_S2 0x800 /* Sign select bit(Out2)*/
-
- /*
- * PA_DRMODE value shift defines. For each of the above bit masks
- * these are the shift values that input data should be shifted by.
- */
- #define _VO2_PA_AP_SHIFT_GFX 0x0
- #define _VO2_PA_AP_SHIFT_FBA 0x3
- #define _VO2_PA_AP_SHIFT_S1 0x5
- #define _VO2_PA_AP_SHIFT_VID 0x6
- #define _VO2_PA_AP_SHIFT_FBB 0x9
- #define _VO2_PA_AP_SHIFT_S2 0xb
-
- /*
- * PA_LOOKUP_TAB mask bits
- */
- #define _VO2_PA_LOOKUP_ENA_F1 0x001
- #define _VO2_PA_LOOKUP_ENA_F2 0x002
- #define _VO2_PA_LOOKUP_ENA_F3 0x004
- #define _VO2_PA_LOOKUP_ENA_F4 0x008
- #define _VO2_PA_LOOKUP_ENA_OUT1 _VO2_PA_LOOKUP_ENA_F2
- #define _VO2_PA_LOOKUP_ENA_OUT2 _VO2_PA_LOOKUP_ENA_F4
-
- /*
- * FB_SRC_SEL value defines ???
- */
- #define _VO2_FB_SRC_D1_1 0x0 /* D1 channel 1 */
- #define _VO2_FB_SRC_D1_2 0x1 /* D2 channel 2 */
- #define _VO2_FB_SRC_ANALOG 0x2 /* Analog */
- #define _VO2_FB_SRC_COMPOSITE 0x3 /* Composite */
- #define _VO2_FB_SRC_FDBK 0x4 /* Feedback */
- #define _VO2_FB_SRC_NULL 0x5 /* NULL */
- #define _VO2_FB_SRC_GFX 0x6 /* GFX */
- #define _VO2_FB_SRC_VME 0x7 /* VME */
-
- /*
- * FB_DST_DEL value defines (preshifted)
- */
- #define _VO2_FB_DST_DIGITAL 0x00 /* Digital Video out */
- #define _VO2_FB_DST_ANALOG 0x00 /* Analog output */
- #define _VO2_FB_DST_NULL 0x08 /* Point to nothing */
- #define _VO2_FB_DST_GFX 0x10 /* GFX Output */
- #define _VO2_FB_DST_TEX 0x10 /* TEX Output */
- #define _VO2_FB_DST_VME 0x18 /* VME Output */
-
- /*
- * FB_COMMAND register bits
- */
- #define _VO2_FB_COMMAND_OW 0x001
- #define _VO2_FB_COMMAND_GPI_OUT_EN 0x002
- #define _VO2_FB_COMMAND_GPI_OUT_1 0x004
- #define _VO2_FB_COMMAND_GPI_OUT_2 0x008
- #define _VO2_FB_COMMAND_FIELD_MODE 0x000
- #define _VO2_FB_COMMAND_FRAME_MODE 0x010
- #define _VO2_FB_COMMAND_UNUSED 0x020
- #define _VO2_FB_COMMAND_W_RESET 0x040
- #define _VO2_FB_COMMAND_R_RESET 0x080
- #define _VO2_FB_COMMAND_LINE_OFFSET_BIT 0x100 /* 0 = 525 , 1 = 625 */
- #define _VO2_FB_COMMAND_LINE_OFFSET_525 0x000 /* 0 = 525 , 1 = 625 */
- #define _VO2_FB_COMMAND_LINE_OFFSET_625 0x100 /* 0 = 525 , 1 = 625 */
- #define _VO2_FB_COMMAND_PACK_MODE 0x200
- #define _VO2_FB_COMMAND_DIG_SEL 0x400 /* 0 = D1_1, 1 = D1_2 */
- /*
- * FB_COMMAND mask
- */
- #define _VO2_FB_COMMAND_RESET 0xc0
- #define _VO2_FB_COMMAND_GPI_OUT 0x0c
-
- /*
- * FIELD_DOMINANCE is a four bit register used to invert the odd/even signal
- * when doing input or output. Fine grained control is provided for maximum
- * flexibility: for bits numbered <3..0>, we have the following:
- *
- * bit <0> inverts the even/odd signal used to derive video input field order;
- * bit <1> inverts the even/odd signal used to derive video output field order;
- * bit <2> inverts the even/odd signal used to determine when to reset for
- * video output;
- * bit <3> inverts the even/odd signal used to clock the VLAN controller.
- * (bits <2> and <3> should probably always match bit <1>).
- */
- #define _VO2_FIELD_DOM_INPUT 0x1
- #define _VO2_FIELD_DOM_OUTPUT 0x2
- #define _VO2_FIELD_DOM_TRIGGER_RESET 0x4
- #define _VO2_FIELD_DOM_VLAN_CLOCK 0x8
-
- /*
- * FB_CLK_PLL_CTL_REG1 defines
- */
- #define _VO2_FB_IN_CLK_RANGE 0x001
- #define _VO2_FB_OUT_CLK_RANGE 0x002
- #define _VO2_FB_IN_CLK_DELAY 0x03c
- #define _VO2_FB_OUT_CLK_DELAY 0x3c0
-
- #define _VO2_FB_IN_CLK_LOW_RANGE 0x000
- #define _VO2_FB_IN_CLK_HIGH_RANGE 0x001
- #define _VO2_FB_OUT_CLK_LOW_RANGE 0x000
- #define _VO2_FB_OUT_CLK_HIGH_RANGE 0x002
- #define _VO2_FB_IN_CLK_ADVANCE 0x018
- #define _VO2_FB_OUT_CLK_ADVANCE 0x0c0
-
- /*
- * FB_CLK_PLL_CTL_REG2 defines
- */
- #define _VO2_IN_CLK_DIVIDE_BY_2 0x0
- #define _VO2_IN_CLK_PASS 0xff
-
- /*
- * FB_OUT_PIPE_DLY
- */
- #define _VO2_FB_OUT_PIPE_DLY_MAX 0xff
-
- /*
- * PA_DRMODE in Alpha blend modes. These values define the bus that
- * is connected to output of the Alpha processor
- */
- #define _VO2_PA_AP_FBA_COLOR 0x0 /* Input 1 */
- #define _VO2_PA_AP_FBA_ALPHA 0x1 /* Input 2 */
- #define _VO2_PA_AP_FBB_ALPHA 0x2 /* Input 3 */
- #define _VO2_PA_AP_FBB_COLOR 0x3 /* Input 4 */
- #define _VO2_PA_AP_BLEND_OUT 0x4 /* Alpha blend output */
- #define _VO2_PA_DR_FB_LUT 0x5 /* F2/F4 LUT output */
-
- /*
- * VO2L_D1_1_CS & VO2L_D1_1_CS register define
- */
- #define _VO2L_D1_4444_DLY_A_MASK 0x03 /* delay on link A */
- #define _VO2L_D1_4444_DLY_B_MASK 0x0c /* delay on Link B */
- #define _VO2L_D1_4444_ENABLE 0x10 /* 4444 enable */
- /*
- * VO2L_D1_1_CS values ...
- */
- #define _VO2L_D1_4444_A_DLY_0_CLK 0x00
- #define _VO2L_D1_4444_A_DLY_1_CLK 0x01
- #define _VO2L_D1_4444_A_DLY_2_CLK 0x02
- #define _VO2L_D1_4444_A_DLY_3_CLK 0x03
-
- #define _VO2L_D1_4444_B_DLY_0_CLK 0x00
- #define _VO2L_D1_4444_B_DLY_1_CLK 0x04
- #define _VO2L_D1_4444_B_DLY_2_CLK 0x08
- #define _VO2L_D1_4444_B_DLY_3_CLK 0x0c
-
- /*
- * Sync Lock type values
- */
- #define _VO2_SYNC_NONBURST_LOCK 0x0
- #define _VO2_SYNC_BURST_LOCK 0x1
-
- /*
- * Sync Level values
- */
- #define _VO2_SYNC_LEVEL_1V 0x0
- #define _VO2_SYNC_LEVEL_4V 0x1
-
- /*
- * Genlock Sync select values
- */
- #define _VO2_SYNC_D1_1 0x0
- #define _VO2_SYNC_D1_2 0x1
- #define _VO2_SYNC_HOUSE 0x2
- #define _VO2_SYNC_COMPOSITE 0x3
- #define _VO2_SYNC_COMPONENT 0x4
- #define _VO2_SYNC_GREEN 0x5
- #define _VO2_SYNC_YC 0x6
- #define _VO2_SYNC_STANDALONE 0x7
-
- /*
- * Delay values for inpath and outpath
- */
- #define _VO2_INPUT_FIR_DELAY 35
- #define _VO2_INPUT_FIR_BYPASS_DELAY 1
- #define _VO2_VIDOUT_FIR_DELAY 34
- #define _VO2_VIDOUT_FIR_BYPASS_DELAY 0
- #define _VO2_MATRIX_DELAY 5
- #define _VO2_OUTPUT_MATRIX_DELAY 6
- #define _VO2_OUTPUT_MATRIX_BYPASS_DELAY 1
- #define _VO2_OUTPUT_VDR_D1OUT_ALPHA_DELAY 31
- #define _VO2_CKG_DELAY 15 /*not determined yet*/
- #define _VO2_PA2_LUT_DELAY 3
- #define _VO2_PA2_PASSTHROUGH_DELAY 2
- #define _VO2_PA2_AP_DELAY 9
- #define _VO2_EAV_DIGITAL_DELAY_525 110
- #define _VO2_EAV_DIGITAL_DELAY_625 116
- #define _VO2_EAV_ANALOG_DELAY_525 93
- #define _VO2_EAV_ANALOG_DELAY_D1525 100
- #define _VO2_EAV_ANALOG_DELAY_625 131
- #define _VO2_EAV_ANALOG_DELAY_D1625 110
- #define _VO2_DIG_SRC_DELAY 17
- #define _VO2_ANLG_SRC_DELAY 15
- #define _VO2_ANALOG525_UPPER_LEFT_X_VALUE 3
- #define _VO2_GFX_SRC_DELAY -1
- #define _VO2_VME_SRC_DELAY_8 0
- #define _VO2_VME_SRC_DELAY_10 1
- #define _VO2_VME_SRC_DELAY_422_10 2
- #define _VO2_VME_SRC_DELAY_422_8 -1
- #define _VO2_OUTPUT_GFX_DELAY 1
- #define _VO2_OUTPUT_TEX_DELAY 4
- #define _VO2_OUTPUT_TEX8_DELAY 6
- #define _VO2_OUTPUT_DIG_VIDEO_DELAY 56
- #define _VO2_OUTPUT_ANLG_VIDEO_DELAY 52
- #define _VO2_OUTPUT_VME_DELAY 3
- #define _VO2_OUTPUT_VME_DELAY_422_8 4
- #define _VO2_INPATH_CRX_DELAY 4
- #define _VO2_INPATH_CONSTANT_DELAY (_VO2_MATRIX_DELAY+_VO2_INPATH_CRX_DELAY)
- #define _VO2_INPATH_ALPHA_CONSTANT_DELAY 0
- #define _VO2_INPATH_Y_525_DELAY 16
- #define _VO2_INPATH_Y_625_DELAY 21
- #define _VO2_COMPOSITE_INPATH_EAV_OFFSET 0
- #define _VO2_COMPOSITE_INPATH_Y_OFFSET_525 0
- #define _VO2_COMPOSITE_INPATH_Y_OFFSET_625 0
- #define _VO2_DIGITAL_INPATH_Y_OFFSET_525 1
- #define _VO2_DIGITAL_INPATH_Y_OFFSET_625 1
-
-
- /* GENOUT DELAYS */
- #define _VO2_LINE_DELAY_HI_525 0x2
- #define _VO2_LINE_DELAY_HI_625 0x3
- #define _VO2_LINE_DELAY_HI_D1525 0x3
- #define _VO2_LINE_DELAY_HI_D1625 0x3
-
- #define _VO2_LINE_DELAY_LO_525 0xfe
- #define _VO2_LINE_DELAY_LO_625 0xa2
- #define _VO2_LINE_DELAY_LO_D1525 0x4c
- #define _VO2_LINE_DELAY_LO_D1625 0x52
-
- #define _VO2_COMP_IN_CLK_DIGITAL 0x00
- #define _VO2_COMP_IN_CLK_NTSC 0x80
- #define _VO2_COMP_IN_CLK_PAL 0xc0
-
- /* VLAN modes (525 and 625) */
-
- #define _VO2_VLAN_NOTRUNNING 0
- #define _VO2_VLAN_525 1
- #define _VO2_VLAN_625 2
-
- #define _VO2_VLAN_READY 0
- #define _VO2_VLAN_DEAD 1
-
- /*
- * Events - these are accumulated in the vo2_data->events field
- * (the bit field definitions match the interrupt mask's)
- */
- #define _VO2_EVENT_XFER_DONE 0x00000001 /* VLTransferComplete */
- #define _VO2_EVENT_XFER_FAIL 0x00000002 /* VLTransferFailed */
- #define _VO2_EVENT_STREAM_START 0x00000004 /* VLStreamStarted */
- #define _VO2_EVENT_STREAM_STOP 0x00000008 /* VLStreamStopped */
-
- #define _VO2_EVENT_VLAN_TIMEOUT 0x00000010 /* VLSequenceLost */
- #define _VO2_EVENT_DMA_TIMEOUT 0x00000020 /* VLSequenceLost */
- #define _VO2_EVENT_FRMDRP_CP 0x00000080 /* VLSequenceLost */
-
- #define _VO2_EVENT_FRMDRP_ALPHA 0x00000100 /* VLSequenceLost */
- #define _VO2_EVENT_FRMREP_ALPHA 0x00000200 /* VLSequenceLost */
-
- #define _VO2_EVENT_FRMDRP_A 0x00040000 /* VLSequenceLost */
- #define _VO2_EVENT_FRMDRP_B 0x00080000 /* VLSequenceLost */
-
- #define _VO2_EVENT_FRMREP_A 0x00100000 /* VLSequenceLost */
- #define _VO2_EVENT_FRMREP_B 0x00200000 /* VLSequenceLost */
-
- #define _VO2_EVENT_NOSYNC_D1_1 0x00400000 /* VLSyncLost */
- #define _VO2_EVENT_NOSYNC_D1_2 0x00800000 /* VLSyncLost */
- #define _VO2_EVENT_NOSYNC_VI 0x01000000 /* VLSyncLost */
- #define _VO2_EVENT_NOSYNC_VO 0x02000000 /* VLSyncLost */
- #define _VO2_EVENT_NOGEN_VI 0x04000000 /* VLSyncLost */
- #define _VO2_EVENT_NOGEN_VO 0x08000000 /* VLSyncLost */
-
- #define _VO2_EVENT_VME_CNTRL 0x80000000 /* No VL Event defined */
-
-
- /*
- * Triggers; for VO2_DMA_TRIGGER ioctl
- */
- #define _VO2_TRIGGER_NONE 0
- #define _VO2_TRIGGER_GPI_1 1
- #define _VO2_TRIGGER_GPI_2 2
- #define _VO2_TRIGGER_VLAN 3
-
- /*
- * GPI output states
- */
- #define _VO2_GPI_OUT_ON 0
- #define _VO2_GPI_OUT_OFF 1
-
-
- #endif /* !__VO2_H__ */
-